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Function Table
CLK L H X X SCLK X X L H SEL L L H H X EN* L L L L H CLKOUT+ L H L H Z*
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PI90LV14/PI90LVT14
1:5 Clock Distribution
Features
* Meets and Exceeds the Requirements of ANSI TIA/EIA-644-1995 * Designed for clocking rates up to 320MHz * Operates from a single 3.3V Supply * Low Voltage Differential Signaling (LVDS) with Output Voltages of 350mV into a 100 load * Choice between LVDS or TTL clock input * Synchronous Enable/Disable * Clock outputs default LOW when inputs open * Multiplexed clock input - Internal 300k pullup resistor on input pins - CLK and CLK have 110internal termination (PI90LVT14) * 50ps Output-to-Output Skew * 475ps typical propagation delay * Bus Pins are high impedance when disabled or with VCC less than 1.5V * TTL inputs are 5V Tolerant * Power Dissipation at 400Mbits/s of 150mW * Function compatible to Motorola (PECL) MC100EL14 and Micrel/Synergy (PECL) SY100EL14V * >9kV ESD Protection * 20-pin TSSOP (L) and QSOP (Q) packages
Description
The PI90LV14 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320MHz with low skew. The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clock or a high-speed system clock. When LOWthe SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. Because the internal flip-flop is clocked on the falling edge of the input clock, all associated specification limits are referenced to the negative edge of the clock input. The intended application of these devices and signaling technique is for high-speed clock distribution between boards.
PI90LV14 Block Diagram
1 2 20 19 VCC
CLK1OUT+ CLK1OUT-
Pin Descriptions
Pin CLK, CLK SCLK EN SEL CLK1- 5OUT Funtion Differential Clock Outputs LVTTL Clock Input Synchronous Enable Clock Select Input Differential Clock Inputs
EN CLK2OUT+ CLK2OUT- 3 4 Q
V
D 18 17
VCC GND
CLK3OUT+ CLK3OUT-
5 6
1
16 15
110 PI90LVT14 Only
SCLK CLK
CLK4OUT+ CLK4OUT-
7 8
0
14 13
CLK GND
12 CLK5OUT+ CLK5OUT- 9 10 11
SEL
GND
* On next negative transition of CLK, or SCLK
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PI90LV14/PI90LVT14 1:5 Clock Distribution
Electrical Characteristics over Recommended Operating Conditions (unless otherwise noted).
Symbol VOD VOD VOC(SS) VOC(SS) VOC(PP) Parame te r Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady- state common- mode output voltage Change in steady- state common- mode output voltage between logic states Peak- to- peak common- mode output voltage Supply Current High- level input current Low- level input current Short- circuit output current VOD = 0V IOZ IO(OFF) CIN CO RTERM High- impedance output current Power- off output current Input capacitance, Output capacitance Termination Resistor VO = 0V or VCC VCC = 1.5V, VO = 2.4V VI = 0.4 sin (4E6t) +0.5V VI = 0.4 sin (4E6t) +0.5V, Disabled PI90LVT14 90 9 pF 10 110 132 Enabled, RL = 100 VIN = VCC or GND Disabled, VIN = VCC or GND IIH IIL IOS VIH = 2V VIL = 0.8V VODOUT+ or VODOUT- = 0V 0.5 See Figure 3 Te s t Conditions RL = 100 See Figures 1 and 2 M in. 247 -50 1.125 -50 60 21 2.5 3.0 5.0 1.40 Typ.(1) 340 M ax. 454 mV 50 1. 7 50 mV 100 35 mA 4.0 20 20 7.4 4.7 1 A 1 A V Units
ICC
mA
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PI90LV14/PI90LVT14 1:5 Clock Distribution
Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)(8,9).
Characte ris tic Propagation Delay to Output CLK to CLKOUT SCLK to CLKOUT SEL to CLKOUT Disable Time CLK or SCLK to CLKOUT Symbol tPLH tPHL M in. Typ. 3.0 2.5 2.6 2.7 2.7 4.7 3.7 M ax. 4.0 3.5 3.6 3.5 3.5 6.0 6.0 TBD TBD TBD 100 100 -100 -100 550 500 0.20 0.125 150 150 200 70 250 1.5 720 720 0.800 VCC - 0.20 1200 1200 300 190 MHz V ps Units Condition
ns
tPHZ tPLZ tPZH tPZL tskew tskew tskew ts ts th th VPP VCMR tr tf tSK1R tSK2R
ns
2
Part- to- Part Skew CLK (Diff) to Q CLK (SE), SCLK to Q With Device Skew Setup Time ENx to CLK CEN to CLK Hold Time ENx, CEN to SCLK ENx, CEN to CLKx M inimum Input Swing (CLK) Com. M ode Range (CLK) Ris e /Fall Time s (20 - 80%) SCLK to CLKOUT SCLK to CLKOUT Duty Cycle Dis tortion Puls e Ske w ( tPLH - tPHL) Channe l-to-Channe l Ske w, s ame e dge M aximum Ope rating Fre que ncy
1
2
2 3 4
ps 5 6 7
Notes: 1. Within-Device skew is defined for identical transitions on similar paths through a device. 2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK. 3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input swings. 4. The range in which the high level of the input swing must fall while meeting the VPP spec. 5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of the output at any given temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage, and temperature. 6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter is guaranteed by design and characterization. 7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak). Output Criteria: 60%/40% duty cycle, VOL (max) 0-4V, VOH (min) 2.7V, Load - 7pF (stray plus probes). 8. CL includes probe and fixture capacitance. 9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
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PI90LV14/PI90LVT14 1:5 Clock Distribution
Parameter Measurement Information
II
DOUT+ DIN VI DOUT- GND
IOY IOZ VOD VODOUT+ VOC VODOUT-
(VODOUT++VODOUT-)/2
Figure 1. Voltage and Current Definitions
DOUT+ Input DOUT- VOD
3.75k 100 3.75k
0V VTEST 2.4V
Figure 2. VOD Test Circuit
3V DOUT+ 49.9 1% (2 places) Input DOUT-
VOC
VI
0V
VOC(PP) VOC(SS)
Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf 1ns, Pulse Repetition Rate (PRR) = 50 Mpps, Pulse width = 10 0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3dB bandwidth of at least 300MHz.
Figure 3. Test Circuit & Definitions for the Driver Common-Mode Output Voltage
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PI90LV14/PI90LVT14 1:5 Clock Distribution
Parameter Measurement Information (continued)
32V 1.4V 0.8V
tPLH VOD 100 1% tPHL
Input DOUT+ Input DOUT-
CL= 10pF (2 places)
Output 0V
VOD(H) VOD(L)
100% 80% 20% 0%
tf
tr
Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf 1ns, Pulse Repetition Rate (PRR) = 15 Mpps, Pulse width = 10 0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Figure 4. Test Circuit, Timing, & Voltage Definitions for the Differential Output Signal
DOUT+ 0.8V or 2V DOUT- Input
49.9 1% (2 places)
VODOUT+ VODOUT-
+ 1.2V -
2V 1.4V Input 0.8V
tPZH VODOUT+
or
tPHZ 1.4V 1.3V 1.2V
VODOUT- tPZL VODOUT-
or
tPLZ 1.2V 1.1V 1V
VODOUT+
Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf 1ns, Pulse Repetition Rate (PRR) = 0.5 Mpps, Pulse width = 500 10ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Figure 5. Enable & Disable Time Circuit & Definitions
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PI90LV14/PI90LVT14 1:5 Clock Distribution
20-Pin QSOP (Q) Package
20
.008 0.20 MIN.
.150 .157
3.81 3.99
Guage Plane
.008 .013 0.20 0.33
.010 0.254
1 .337 8.56 .344 8.74
Detail A
.016 .035 0.41 0.89
.041 1.04 REF
0-6
.058 REF 1.47
.053 1.35 .069 1.75 SEATING PLANE
.015 x 45 0.38
Detail A
.007 .010 .016 .050 0.41 1.27
0.178 0.254
.025 BSC 0.635
.004 0.101 .010 0.254 .008 0.203 .012 0.305
.228 .244 5.79 6.19
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
20-Pin TSSOP (L) Package
20
.169 .177
4.3 4.5
1 .252 .260 6.4 6.6 .004 0.09 .008 0.20 .047 1.20 Max 0.45 0.75 .018 .030
SEATING PLANE
.238 .269 6.1 6.7
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 0.05 .006 0.15
X.XX X.XX
DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS
Ordering Information
Orde ring Code PI90LV14L PI90LVT14L PI90LV14Q PI90LVT14Q Package Type 20- Pin 173- mil TSSOP -40C to 85C 20- Pin 150- mil QSOP Orde ring Range
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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